Speed and memory optimised interleaving

ABSTRACT

This invention relates to a method for interleaving, according to an interleaving scheme, an input sequence comprising K bits into an interleaved sequence, comprising the steps of (a) storing the input sequence in a first memory means, (b) generating first indices of N succeeding bits of the interleaved sequence, wherein 1 m(F) N m(F) K, (c) converting, according to an inverse of said interleaving scheme, said first indices into second indices indicative of the positions where said N succeeding bits of the inter-leaved sequence are stored in said first memory means, and (d) reading out said N succeeding bits from said positions in said first memory means, thereby generating at least part of said interleaved sequence.

FIELD OF THE INVENTION

The present invention relates to interleaving in a digital communicationsystem, and in particular to speed and memory optimized interleaving.

DESCRIPTION OF THE PRIOR ART

A transmitter for use in a digital telecommunication system is known,for instance, from 3GPP TS 25.212 V3.4.0 (2000-09) “3rd GenerationPartnership Project; Technical Specification Group Radio Access Network;Multiplexing and channel coding (FDD) (Release 1999)”, section 4.2. InFIG. 1 a of the present application, a block diagram of parts of such atransmitter is given. As shown, the transmitter includes a channelencoder, a rate matcher, an interleaver, and a modulator. Furthercomponents (for frequency up-conversion, amplification etc.) are omittedfor reasons of conciseness.

CHANNEL ENCODER: The channel encoder, also referred to as forward errorcorrection (FEC) encoder, adds redundant information to each incomingdata block. Thereby, the size (length) of the data block increases fromK “uncoded” bits, at the encoder input, to L>K “coded” bits at itsoutput. Herein, the size L of the coded data block depends on, at least,the number K of uncoded bits (in the uncoded data block) and a parameterr commonly referred to as the coding rate. With values in the range of0<r<1, the coding rate r provides an indication of the degree (extent,scope) of redundancy introduced by the channel encoder: the smaller thevalue of r, the more redundant information is added.

The way, in which redundant information is generated, depends on thechannel coding scheme employed. Typical examples are convolutionalcoding, concatenated convolutional coding such as “turbo” coding, andblock coding. Turbo coding will be described below in more detail.

INTERLEAVER: The purpose of the interleaver is to change the order(rearrange) of data bits inside each coded data block in order to ensurethat a temporary disturbance during transmission of the data block overthe physical channel does not lead to a loss of many adjacent coded databits, since such a loss in many cases would be unrecoverable at thereceiver side. A simple form of interleaving can be obtained by writingan input sequence into an interleaving matrix (memory) in a row-by-rowmanner and by then reading out therefrom in a column-by-column fashion(or vice-versa). For more sophisticated interleaving variants, so-calledpermutation “patterns” are commonly used in order to indicate thechanges to be performed in the order of bits by providing a relationshipbetween input and output bit positions.

MODULATOR etc.: Upon interleaving, the (baseband) modulator converts theinterleaved data bits into symbols which, in general, arecomplex-valued. Further components, such as digital-to-analogconversion, frequency up-conversion and amplification are not shown inFIG. 1 a for conciseness reasons. Finally, a signal is transmitted overthe physical channel (air interface, wireline etc.).

Typically, the channel encoding scheme, the inter-leaving scheme, andthe modulation scheme are specified in detail by a standard according towhich the telecommunication system is to be operated. For example, inthird generation (3G) mobile communication standards such as WCDMA(wideband code division multiple access), two channel coding schemes arespecified apart from the “no coding” case: convolutional coding andturbo coding. With these coding schemes, several coding rates are to beused (r=½, r=⅓, and others). Also, the uncoded data blocks supplied tothe channel encoder may have different sizes K. For these reasons, 3Gsystems will have to support many different coded data block sizes L_i,i=1, 2, . . . also referred to as different “transport channel types”,wherein the block sizes may vary over a wide range (from a few bits tomore than 10000 bits, e.g.). On the other hand, due to differentphysical channel sizes, several interleaving schemes with differentinterleaver sizes Q_j, j=1, 2, . . . may have to be supported. Forexample, the WCDMA standard specifies seven different interleaver sizesin the uplink and 17 in the downlink.

In order to match the channel encoder output to a given time slot and/orframe structure, several transport channel types with different (butmaybe similar) coded data block sizes L_i should use the same physicalchannel type (having a given size referred to as target block size inthe following).

RATE MATCHER: For this to become possible, a rate matcher is typicallyinserted between the channel encoder and the interleaver, as shown inFIG. 1 a. Although it is clear from the above, that a singlecommunication system may have to support several or even manycombinations of coded data block sizes L_i and target block sizes Q_j,the following generic description is based, for conciseness reasons, ona single combination of a coded data block size L and a target blocksize Q. In each coded data block, the rate matcher shown in FIG. 1 aeither repeats or deletes (removes, “punctures”) a certain number ofbits in order to obtain a rate-matched data block having a given targetblock size of Q bits (which is, e.g., the size of an interleaver or aparticular block length required for transmission). For this purpose,the rate matcher has to repeat A=Q−L bits of the coded data block, if Lis inferior to Q, or to remove (puncture) L−Q=−A bits therefrom, if L issuperior to Q, so as to adapt the block size L to said target block sizeQ. In cases where Q=L, no adjustment in size is necessary, of course.

The positions inside each coded data block, where bits are to berepeated or deleted, are also specified in detail by the standard. Withthe knowledge of these positions, the receiver will be able toreconstruct a decoded data block from the received data block.

TURBO CODER: As an example for a channel encoder, FIG. 1 b shows a turbocoder (TC). Turbo coding is a powerful channel coding method used, forinstance, for 3G data services requiring high qualities of service. Asis well-known in the art, a turbo coder is a parallel concatenatedconvolutional coder with at least two constituent encoders and one turbocode interleaver. While the output bits of the constituent encodersusually are referred to as “parity” bits, turbo coders also output theinput data “as is”. These unaltered output bits of a channel encoder arecommonly referred to as “systematic” bits. For the turbo coder (TC)shown in FIG. 1 b, an exemplary coding rate of r=⅓ was chosen, so thatfor each input bit, a total of three output bits is generated. Theparity bit sequences are generated by the first and second constituentencoders receiving an original and interleaved version, respectively, ofthe input sequence (uncoded data block), while the systematic bits arepassed along the upper horizontal line. It is assumed in FIG. 1 b thatthe encoder output bits are multiplexed into a single bit stream by aswitch. However, this multiplexing is for illustrative purposes only.Alternatively, the channel encoder could generate parallel outputstreams.

WCDMA TC INTERLEAVER: Consider the TC-internal interleaver designated“TC-interl.” in FIG. 1 b. According to the WCDMA standard, theinterleaving scheme for this interleaver is specified as a sequence ofsteps:

-   1. Determine the number R of rows and the number C of columns of the    interleaving matrix necessary for interleaving an input sequence    comprising K bits,-   2. Write said input sequence into said R×C interleaving matrix in a    row-by-row manner,-   3. Determine the intra-row permutation patterns (depending on the    row number) and perform the corresponding intra-row permutation    operations,-   4. Determine the inter-row permutation pattern (one and the same    pattern for all columns) and perform the corresponding inter-row    permutation operations,-   5. Read from said R×C interleaving matrix in a column-by-column    manner, thereby generating the interleaved sequence.

Herein, the steps 1-5 include the following operations:

Step 1 (determine R, C): Since the number K of bits in the inputsequence (to the TC interleaver) may range from 40 to 5114 bits, thestandard specifies a procedure for determining the number R of rows andthe number C of columns in the interleaving matrix on the basis of thevalue of K. More precisely, there can be R=5, 10, or 20 rows in thematrix, depending on the value of K. The determination of the value of Cinvolves the search for a minimum prime p. Herein, p may assume 52different values ranging from 7 to 257.

Step 2 (write in row-by-row): Once R and C are determined, the inputsequence comprising K bits is written into the R×C interleaving matrixin a row-by-row manner starting with the first row (usually having anindex of zero).

Step 3 (intra-row permutations): In the third step, an intra-rowpermutation pattern must be determined for each row before the intra-rowpermutation operations can take place. For this purpose, a primitiveroot g0 must be selected from a table in dependence of said minimumprime p. Given the values of g0 and p, base sequences c(i), i=1, 2, . .. , p−2 can be determined recursively using modulo operations. Then, aminimum prime integer set {q(1), . . . , q(R−1)} is determined such thatthe greatest common divisor of q(j) and p−1 is equal to one, whereinq(j)>6, q(j)>q(j−1) and q(0)=1. Finally, the set {q(0), . . . , q(R−1)}is permuted so as to generate a new set {p(0), . . . , p(R−1)} such thatp(P(j))=q(j), wherein j=0, 1, . . . ,R−1 and P(j) denotes the inter-rowpermutation pattern determined in step 4 (see below). Then, theintra-row permutation pattern {c_(j)(0), c_(j)(1), . . . , c_(j)(p−2)}for the j-th row is determined as a base sequence, wherein the indexdepends on i, p(j) and p as follows:c _(j)(i)=c([i*p(j)]mod[p−1])  (1)Herein, c_(j)(i) is the input bit position of the i-th output bit afterthe permutation of the j-th row.

Step 4 (inter-row permutations): In step 4, the inter-row permutationpattern must be determined before performing the correspondingpermutation operations. For this purpose, depending on the values of Kand R, one of the following four patterns P_(X)={P(0), P(1), . . . ,P(R−1)} is selected (X=A, B, C or D), wherein P(j) is the original rowindex of the j-th permuted row. $\begin{matrix}{{P_{A} = \left\{ {19,9,14,4,0,2,5,7,12,18,10,8,13,17,3,1,16,6,15,11} \right\}},{P_{B} = \left\{ {19,9,14,4,0,2,5,7,12,18,16,13,17,15,3,1,6,11,8,10} \right\}},{P_{C} = {{\left\{ {9,8,7,6,5,4,3,2,1,0} \right\}\quad{for}\quad R} = 10}},{P_{D} = {{\left\{ {4,3,2,1,0} \right\}\quad{for}\quad R} = 5.}}} & (2)\end{matrix}$

Both P_(A) and P_(B) can be selected for R=20, depending on the value ofK.

Step 5 (read out column-by-column): In the final step, the R×Cinterleaving matrix containing the bits permuted in steps 3 and 4 isread out in a column-by-column manner starting with the first column(usually having an index of zero). If the number R*C of positions in theinterleaving matrix exceeds the number K of bits in the input sequence,a total of R*C−K bits must be pruned (removed) from the sequence thusgenerated.

INTERLEAVER IMPLEMENTATIONS: As the skilled person will readilyappreciate, there are two basic approaches to an interleaverimplementation where the interleaving scheme is specified in the form ofan algorithm as the one described above.

-   1. Determine interleaving patterns during the inter-leaving process    as such: In accordance with this approach, denoted A1, the period of    time in which interleaving patterns are determined overlaps to a    large degree the period of time in which permutation operations are    actually performed. In the above example, this would imply to    determine R and C first (step 1). Then, the input sequence would be    written into the interleaving matrix (step 2). Thereafter, each    intra-row permutation pattern would be determined just before    performing the corresponding permutation operations (step 3) so    that, when considering the entire intra-row permutation process, the    periods of time for determining all intra-row patterns and for    performing all intra-row permutation operations, coincide to a large    extent. Then, the inter-row permutation pattern would be determined    so as to be able to perform the inter-row permutation operations    (step 4). Finally, the interleaving matrix would be read out (step    5).

In summary, it can be stated that according to approach A1, theoperations not directly affecting the bits to be interleaved (such asthe operations for determining permutation patterns) and those actuallyaffecting said bits (such as the actual interleaving operations) areperformed in essentially the same period of time.

-   2. Determine interleaving patterns before performing interleaving    operations: In this approach, termed A2, the operations for    determining the interleaving patterns are separated in time from the    actual inter-leaving operations. This is to say that before the    input sequence is actually processed, all interleaving patterns are    determined (parts of steps 3 and 4). For each output bit position,    the corresponding input bit position is then stored in a position    memory so that, once the input sequence has been written into the    interleaving matrix (step 2), the interleaved sequence can easily be    generated by reading out the bits stored in the interleaving matrix    in the order indicated by the positions stored in the position    memory.

In summary, according to approach A2, the operations not directlyaffecting the bits to be interleaved (such as the operations fordetermining permutation patterns) and those actually affecting said bits(such as the actual interleaving operations) are performed in subsequentperiods of time.

Due to the fact that, in accordance with approach A1, all bits of theinput sequence must be written into the interleaving matrix (memory) atotal of three times (writing into the interleaving matrix two times forpermuting in steps 3 and 4 in addition to the initial writing in step 1)before the interleaved sequence can be read out, the approach A1 revealsa rather high delay, defined as the time period between “last bit in”and “first bit out”. In addition, the determination (i.e. calculation)of the permutation patterns in steps 3 and 4 further contributes to thisdelay, because it takes place in essentially the same period of time asthe actual permutation operations. On the other hand, the approach A1does not require an undue size of memory for storing “interim results”such as permutation patterns or other auxiliary parameter values,because they are determined successively as (and only when) required.

In contrast, approach A2 is very memory demanding while delays aremodest. Given the fact, that in 3G standards such as WCDMA, the maximumlength K of the input sequence amounts to 5114 bits, each position to bestored for later retrieval requires the following number of bits:log₂ 5114=12.32=>13 bits/position.  (3)Furthermore, a total of 163 different interleavers (interleavingschemes) is specified in WCDMA with an average length of the inputsequence of 2500 bits. Therefore, the total number of positions to bestored amounts to163*2500=407500=>407500 positions.  (4)The total number of bits necessary to store all positions for allinterleavers can easily be calculated by multiplying the values obtainedin equations (3) and (4):407500 positions*13 bits/position=5297500 bits.  (5)In addition to the “data” memory needed anyway for storing the inputsequence, A2 thus requires a position memory capable of storing at least5 Mbit.

In existing implementations, the interleaved sequence is outputbit-serially by the interleaver. In view of the high bit rates specifiedin standards such as WCDMA and considering typical hardware complexityand thus cost requirements, it is not possible to serially process thebits at these high bit rates. In other words, existing interleavingimplementations do not support a parallel processing of bits which is aprerequisite to meeting future throughput and delay requirements, as thefollowing example will show. The WCDMA standard specifies services foruser data rates of up to 2 Mbit/s. Given the fact that typicalimplementations are required to support many channels, interleavingwould need to operate at a clock rate of 256 MHz. At this clock rate, itwould be very difficult to implement the interleaver in FPGA (fieldprogrammable gate array) or ASIC (application specific integratedcircuit) technology. If, however, a 4 bit parallel processing waspossible, the clock rate could be reduced to 64 MHz. The skilled personwill readily appreciate that, at this clock rate, the interleaver couldbe implemented in FPGA or ASIC technology.

As already outlined above, according to 3G mobile communicationstandards such as WCDMA, interleavers will have to be implemented formany different lengths K of the input sequences and/or many differentbit rates. A straightforward solution to this problem would consist inimplementing several interleavers according to the prior art and operatethem in a parallel manner (different interleavers for different lengthsK and/or bit rates). However, such an implementation would lead to alarge and complex control logic (using a plurality of counters,memories, etc.) for controlling which input sequence has to be inputinto which interleaver and for assembling the outputs of theinterleavers into a single stream of data. In other words, theimplementational effort in terms of the required hardware would exceedtypical limitations given for FPGA/ASIC circuits or defined printedcircuit board sizes for 3G transceivers.

In view of the above, an interleaver implementation should meet thefollowing requirements:

-   a) it should minimize the delay as measured for instance in terms of    the time difference between “last bit in” and “first bit out”;-   b) it should minimize hardware complexity; in particular, the size    of the required memory should be minimized;-   c) it should be capable of coping with a large variety of lengths K    of the input sequence varying over a wide range; for example, 3G    standards such as WCDMA specify a multitude of K values ranging from    40 to 5114 bits;-   d) it should be capable of coping with high input and output bit    rates; together with requirement a), such high bit rates may lead to    clock rates of 256 MHz;-   e) preferably, it should lend itself to a parallel implementation.

SUMMARY OF THE INVENTION

In view of the above, the object of the invention is to develop improvedinterleaving methods and apparati for interleaving, according to aninterleaving scheme, an input sequence comprising K≧2 bits into aninterleaved sequence.

According to the present invention, this object is achieved by aninterleaving method having the features of claim 1 and a computerprogram product having the features of claim 10. It is also achieved byan interleaving unit and an interleaving apparatus having the featuresof claims 11 and 19, respectively.

According to one aspect of the present invention, first indices of Nsucceeding bits of the interleaved sequence are generated and thenconverted, according to an inverse (reverse) of said interleavingscheme, into second indices indicative of the positions where said Nsucceeding bits of the interleaved sequence are stored in a first memorymeans (RAM, registers etc.) when (once) they are stored therein. Thisis, looking at the (not yet known) interleaved sequence, the indices(“first indices”) associated with N succeeding bits are generated, i.e.these N bits may or may not be adjacent (neighboring), but they followeach other directly or indirectly so that the first indices will havevalues which increase somehow (with or without gaps). It is to be notedthat N is selectable from values in the range of 1, 2, . . . , K so thatboth the entire interleaved sequence can be considered (N=K) andarbitrary parts thereof (N<K). Then, the positions where the consideredN bits are stored (or will be stored upon writing in) in said firstmemory means are determined. These positions are indicated by saidsecond indices. Finally, once these positions are known and the inputsequence has been stored in (written into) the first memory means, theconsidered N bits can be read out from said positions in said firstmemory means, thereby generating, depending on the value of N, at leastpart of the interleaved sequence.

In summary, it can thus be stated that the index calculations areseparated from the actual permutation operations which occur in thefinal process of reading out only. This advantageously allows to reducethe delay between the time instants of writing in the last input bit andreading out the first output bit. It is to be noted that this reductionin delay does not come at the expense of an increased hardware effortbecause of the free selectability of N and the modest hardware effortnecessary for generating and converting indices.

According to another aspect of the present invention, said first memorymeans is organized in a matrix form comprising rows and columns, andtherefore, the first and second indices can be decomposed into row andcolumn indices each. This allows to separately convert first into secondrow indices on the one hand and first into second column indices on theother hand, thereby further reducing hardware complexity. This is due tothe fact that hereby a two-dimensional interleaving problem has beendecomposed into two one-dimensional problems (inter-row and intra-rowpermutations) while still keeping the benefits due to the separation ofthe index calculations and the permutation operations.

According to other aspects of the present invention, hardware complexitycan be reduced further by pre-calculating and storing selected interimresults required for the conversion of the row or column indices.Herein, the interim results are selected such that the hardware effortnecessary for storing said interim parameters does not outweigh thehardware effort necessary for processing said interim results so as toobtain the second indices.

According to another aspect of the present invention, N is selected tohave a value of essentially K/M with M≧2 denoting a sub-sampling factor.Herein, said first memory means is adapted to generate an outputsequence representing one of M polyphases of said interleaved sequencewhen said N succeeding bits are read out from said positions. Asub-sampled version of the interleaved sequence is thus generatedaccording to the principles described above. As the output sequencecorresponds to the interleaved sequence sub-sampled by a factor of M(and having a given phase), this allows to advantageously operate Minterleaving units in parallel. It is to be noted that the expression “avalue of essentially K/M” refers to integer values in the close vicinityof the precise value of K/M.

According to another aspect of the present invention, the processes ofgenerating and converting indices are executed, at least partially,before the input sequence is stored in the first memory means. Thisadvantageously allows to further reduce the delay. In this way, thedelay can be reduced to almost zero by determining the second indicesbefore the input sequence has been entirely written into the firstmemory means.

According to another aspect of the present invention, an interleavingapparatus is provided. It includes M≧2 interleaving units as describedabove, each adapted to receive said input sequence and to generate anoutput sequence representing a different one of said M polyphases, acombiner connected to said M interleaving units for combining the outputsequences generated by said M interleaving units into said interleavedsequence, and a control unit for controlling the operations of said Minterleaving units and said combiner.

This advantageously allows to cope with high input/output bit rateswhile still keeping the necessary hardware effort at an acceptable leveland without sacrificing on the side of the delay properties.

According to another preferred embodiment, there is provided a computerprogram product directly loadable into the internal memory of acommunication unit comprising software code portions for performing theinventive interleaving method when the product is run on a processor ofthe communication unit.

Therefore, the present invention is also provided to achieve animplementation of the inventive method on computer or processor systems.In conclusion, such implementation leads to the provision of computerprogram products for use with a computer system or more specifically aprocessor comprised in e.g., a communication unit.

DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the present invention will, by way of example,be described in the sequel with reference to the following drawings.

FIG. 1: Block diagram of a transmitter (a) and a turbo coder (b)according to the prior art;

FIG. 2: Block diagram of a radio communication system according to thepresent invention;

FIG. 3: Block diagram of a transceiver in a radio communication systemaccording to the present invention;

FIG. 4: Flow chart of an interleaving method according to the presentinvention;

FIG. 5: Flow chart of an alternative interleaving method according tothe present invention;

FIG. 6: Block diagram of an interleaving unit according to the presentinvention;

FIG. 7: Block diagram of an alternative interleaving unit according tothe present invention;

FIG. 8: Block diagram of an interleaving apparatus comprising parallelinterleaving units according to the present invention;

FIG. 9: Block diagram of a row index conversion unit according to thepresent invention;

FIG. 10: Block diagram of a column index conversion unit according tothe present invention.

In the following description, the same reference numerals are used inorder to indicate that the respective block or step has the same (orsimilar) functionality.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2 shows a digital radio telecommunication system according to theinvention. A typical application of such a system is to connect a mobilestation or mobile terminal (MT) 1 to a core network such as the publicswitched telephone network (PSTN) 4. For this purpose, the mobileterminal 1 is connected to a base station (BS) 3 via a radio link 2. Theradio telecommunication system provides a plurality of base stationswhich, through other network nodes such as controllers, switches and/orgateways (not shown) are connected to the PSTN 4. Each base stationtypically supports, at any one time, many radio links 2 towardsdifferent mobile terminals 1.

The radio telecommunication system shown in FIG. 2 could for instance beoperated according to cellular mobile communication standards such asGSM, PDC, TDMA, IS-95, WCDMA. It should however be mentioned that theinvention generally applies to digital telecommunication systems nomatter whether they are radio (i.e. wireless) or wirelinetelecommunication systems. Moreover, the invention also applies touni-directional (“one-way”) communication systems such as broadcastingsystems.

FIG. 3 shows a block diagramme of a transceiver used in mobile terminalsand base stations. Both the mobile terminal 1 and the base station 3 areequipped with one (or several) antenna(s) 5, an antenna duplex filter 6,a radio frequency receiver part 7, a radio frequency transmitter part 8,a baseband processing unit 9 and an interface 10. In case of a basestation, the interface 10 is an interface towards a controllercontrolling the operation of the base station, while in case of a mobileterminal, the interface 10 includes a microphone, a loudspeaker, adisplay etc., i.e. components necessary for the user interface.

The present invention relates to the baseband processing unit 9, partsof which have already been described above with respect to FIGS. 1 a and1 b. The skilled person will readily appreciate that instead oftransceivers each having a common baseband processing unit for both thetransmission and the reception branches, in uni-directional(broadcasting) communication systems, there are transmitters eachincluding a first baseband processing unit for the transmission branchonly and separate receivers each including a second baseband processingunit for the reception branch only. Principally, the invention appliesto any such kind of baseband processing units.

More particularly, the present invention relates to interleavingperformed in the baseband processing unit 9. Such interleaving may beperformed at any stage in the baseband processing unit such as betweenthe channel encoder and the modulator (see the interleaver block of FIG.1 a), within the channel encoder (see FIG. 1 b), or even in thereception branch of the baseband processing unit (not shown).

The person skilled in the art will also appreciate that such basebandprocessing units can be implemented in different technologies such asFPGA (field programmable gate array), ASIC (application specificintegrated circuit), DSP (digital signal processor) or other processortechnology. In these cases, the functionality of such basebandprocessing units is described (and thus determined) by a computerprogram written in a given language such as VHDL, C or Assembler whichis then converted into a file suitable for the respective technology.

The concept underlying the improved interleaving approach according tothe invention will be explained in the following. It is assumed that aninput sequence comprising a number K of bits is to be interleaved,according to a given interleaving scheme, into an interleaved sequence(also comprising K bits). The input sequence may comprise coded bitsoutput by a channel encoder or a rate-matcher (see FIG. 1 a), uncodedbits to be encoded (FIG. 1 b) or any other kind of bits encountered in atransmitting or receiving branch of a baseband unit.

FIG. 4 shows a flow chart of the interleaving method according to theinvention. In a first step 41, said input sequence is stored in a memorysuch as a RAM.

In a second step 42, indices of N succeeding bits of the interleavedsequence are generated, wherein 1≦N≦K. This is, considering the (yetunknown) interleaved sequence, the indices of N succeeding bits arecreated. These indices will be referred to as the first indices ia inthe sequel. For example, in the case of N=K, the first indices may havethe values of, e.g., ia={0, 1, 2, . . . , K−1} or {1, 2, 3, . . . , K},depending on whether the first bit of the interleaved sequence isindexed with a value of zero or one. For N=K/2, they may for instancehave the values of ia={0, 2, 4, . . . , K−2} or {0, 2, 4, . . . , K−1}depending on whether K is even or odd, respectively. Preferably, thefirst indices ia are spaced equidistantly, as shown by the aboveexamples, although in principle any pattern is possible. At the limit, asingle (N=1) first index ia may be generated having a particular value.

In general, the first indices ia must relate to succeeding bits of theinterleaved sequence so that the first indices will have an increasingorder with higher values indicating “later” bits of the interleavedsequence. However, in case the memory is organized in a matrix form(this case will be dealt with below), it may be preferable to expressthe first indices in the form of row and column indices so that it isdifficult to speak of an increasing order in the first indices.Therefore, emphasis must be attached to the fact that the first indicesia relate to succeeding (but not necessarily adjacent/neigh-boring) bitsin the interleaved sequence.

In a third step 43, the first indices ia are converted into secondindices ib according to the inverse of said interleaving scheme. Herein,the second indices ib indicate the positions where said N succeedingbits of the interleaved sequence are stored in the memory.

In a fourth step 44, said N succeeding bits of the interleaved sequenceare read out from these positions in the memory. Thereby, at least partof said interleaved sequence is generated, depending on the value of N.For N=K, the full interleaved sequence comprising K bits is generated instep 44, while for N<K, only that part of the interleaved sequence isgenerated which is identified by the first indices ia. In case ofequidistantly spaced first indices ia, a subsampled version of theinterleaved sequence is generated. Depending on the value of the firstone of said first indices ia, this version has a particular phase andcan thus be referred to as one of the polyphases of the interleavedsequence.

As the skilled person will readily appreciate, step 41 could also beexecuted after (or during) step 42 or even after (or during) step 43. Inthe latter case, the index calculations (steps 42 and 43) would beperformed before (or while) storing the input sequence (step 41).Clearly, step 41 must be executed before step 44, however.

FIG. 5 provides a preferred embodiment of the inter-leaving methoddescribed above with respect to FIG. 4. Herein, it is assumed that thememory is organized in a matrix form, wherein each memory location isindexed (can be addressed) by a row index and a column index. For thisreason, said first and second indices, explained above with respect toFIG. 4, also comprise row and column indices. In particular, it isassumed in FIG. 5 that the first indices ia comprise first row indicesra and first column indices ca, while the second indices ib comprisesecond row indices rb and second column indices cb. Depending on whethercolumn-wise or row-wise reading out/writing in is required, the relationbetween a first index ia as explained above with respect to FIG. 4 andcorresponding ones of the first row indices ra and the first columnindices ca can be expressed asia=ca*R+ra;  (6) oria=ra*C+ca,  (7)wherein R and C denote the number of rows and columns in theinterleaving matrix (memory), ra ranges from 0 to R−1 and ca ranges from0 to C−1. As the skilled person will appreciate, a correspondingrelation links the second row and column indices (rb,cb) with the secondindices (ib).

The steps 51, 52, and 54 in FIG. 5 correspond to the steps 41, 42, and44, respectively, shown in FIG. 4. However, instead of generating“linear” first indices ia (step 42 of FIG. 4), first row and columnindices (ra, ca) are now generated in step 52 of FIG. 5. Similarly, theindex conversion step 53 still converts first (row and column) indicesinto second (row and column) indices indicative of the positions wherethe N succeeding bits are stored in the memory. However, it now includestwo substeps 55 and 56. In the first substep 55, the first row indicesra (generated in step 52) are converted into the second row indices rbsuch that, when executing said step of reading out (step 54), aninter-row permutation operation (the same for all columns) is performedfor those bits of the interleaved sequence identified by said first rowand column indices ra, ca. In a second substep 56, which is executedafter substep 55, the first column indices ca (generated in step 52) andthe second row indices rb (generated in step 55) are converted into thesecond column indices cb such that, when executing said step of readingout (step 54), an intra-row permutation operation depending on the rowindex is performed for the bits of the interleaved sequence identifiedby said first row and column indices ra, ca. The second row and columnindices rb, cb are of course equivalent to the second indices ib, asexplained above.

As the skilled person will readily appreciate, the substeps 55 and 56will depend on the interleaving scheme which is typically specified in astandard. For example, FIG. 5 is adapted to the WCDMA standardspecifying that, first, an intra-row permutation operation has to beperformed, wherein the permutation pattern depends on the row number(i.e. it may be different for each row) and, secondly, an inter-rowpermutation operation is to be performed using the same permutationpattern for all columns, as described above with respect to the priorart. Of course, other variants can easily be conceived. If, for example,an inter-row permutation is to be performed before an intra-rowpermutation, the second column indices would have to be determinedbefore the second row indices. Similarly, an additional input may benecessary for the substeps where a permutation pattern is not to be thesame for all rows or columns. For these reasons, the features of step 53which very much depend on the interleaving scheme and thus are optional,i.e. the second row indices in step 56, are shown in brackets.

Before providing more detail on the row index conversion and the columnindex conversion, some interleaving apparati adapted to execute thesteps of the interleaving methods described above with respect to FIGS.4 and 5 will be described with reference to FIGS. 6 to 8.

FIG. 6 shows a block diagram of an interleaving unit (ILU) 60 adapted toexecute the steps of the interleaving method described above withrespect to FIG. 4. It includes an index generator 61, an indexconversion unit 62 connected to said index generator 61, and a memorymeans 63 connected to said index conversion unit 62 as well as to theinput and the output terminals of said ILU 60.

The index generator 61 is adapted to generate the first indices ia asdescribed above with respect to step 42 of FIG. 4. It may include one orseveral counters or similar devices. The index conversion unit 62 issuitable for converting first indices ia into second indices ib asdescribed above with respect to step 43 of FIG. 4. The memory means 63(such as one or several RAMS, registers etc.) is adapted to receive andstore said input sequence comprising K bits (cf. step 41 of FIG. 4). Anoutput sequence can be retrieved (i.e. read out) from the memory means63 (and thus from the ILU 60) by addressing it with the second indicesib output by the index conversion unit 62. Herein, the output sequencecomprises at least part of said interleaved sequence, depending on thevalue of N, as described above with respect to step 44 of FIG. 4.

As described above with respect to FIG. 4, the input sequence can bestored in the memory means 63 before, during, or after the secondindices are output by the index conversion unit 62. Reading out from thememory means 63 can however be done only after the second indices havebeen output, of course.

FIG. 7 provides a preferred embodiment of the interleaving unitdescribed above with respect to FIG. 6. It shows a block diagram of aninterleaving unit (ILU) 70 adapted to execute the steps of theinterleaving method described above with respect to FIG. 5. Just as inFIG. 5, it is assumed in FIG. 7 that the memory is organized in a matrixform having R rows and C colums and that the first and second indiceseach comprise row and column indices, as described above with respect toFIG. 5.

In accordance with the ILU 60 of FIG. 6, the ILU 70 shown in FIG. 7includes an index generator (71), an index conversion unit (72)connected to said index generator, and a memory means (73) connected tosaid index conversion unit as well as to the input and the outputterminals of said ILU 70.

However, in contrast to FIG. 6, both the first and the second indicescomprise row and column indices in FIG. 7. For this reason, the indexgenerator 71 is adapted to execute step 52 of FIG. 5 (rather than step42 of FIG. 4), i.e. to generate the first row indices ra and the firstcolumn indices ca. Preferably, it therefore include at least twocounters or similar devices. Likewise, while still converting firstindices into second indices indicative of the positions where the Nsucceeding bits are stored in the memory, the index conversion unit 72is adapted to execute step 53 of FIG. 5 (rather than step 43 of FIG. 4),i.e. to convert first row and column indices into second row and columnindices. For this purpose, it includes a row index conversion unit 74and a column index conversion unit 75, each connected to both the indexgenerator 71 and the memory means 73 (see FIG. 7).

Herein, the row index conversion unit 74 is adapted to convert the firstrow indices ra generated by the index generator 71 into the second rowindices rb such that, when reading out said memory, an inter-rowpermutation operation (the same for all columns) is performed for thosebits of the interleaved sequence identified by said first row and columnindices ra, ca. In other words, the row index conversion unit 74 isadapted to execute step 55 of FIG. 5.

The column index conversion unit 75 is adapted to convert the second rowindices rb generated by said row index conversion unit 74 and the firstcolumn indices ca generated by the index generator 71 into the secondcolumn indices cb such that, when reading out said memory, an intra-rowpermutation operation depending on the row index is performed for thebits of the interleaved sequence identified by said first row and columnindices ra, ca. For this reason, the column index conversion unit 75,which is thus adapted to execute step 56 of FIG. 5, is also connected tothe row index conversion unit 74.

The second row and column indices rb and cb are then output by the units74 and 75, respectively, in order to address the memory means 73 so asto generate the output sequence.

Similar to the details of the step 53 shown in FIG. 5, the details ofthe index conversion unit 72 depend on the specified interleavingscheme. For the details of the index conversion unit 72 of FIG. 7, theWCDMA standard was assumed with its sequence of ‘intra-row permutationwith varying patterns, then inter-row permutation with the same pattern’as described above with respect to FIG. 5. For this reason, the columnindex conversion unit 75 requires the second row indices rb (determinedby the row index conversion unit 74) as an input in addition to thefirst column indices ca in order to be able to determine the secondcolumn indices cb, while said row index conversion unit 74 directlyconverts the first into the second row indices without requiring furtherindices. Of course, other variants can easily be conceived for the indexconversion unit 72. If, for example, an inter-row permutation usingvarying patterns is to be performed before an intra-row permutationusing the same pattern, the second column indices cb output by thecolumn index conversion unit 75 would have to be input into the rowindex conversion unit 74 to enable it to convert the first row indicesra into the second row indices rb. For these reasons, the features ofthe index conversion unit 72 which very much depend on the interleavingscheme and thus are optional, i.e. the rb input to the column indexconv. unit 75, are indicated by dashed lines in FIG. 7.

FIG. 8 shows a block diagram of an interleaving apparatus 80 accordingto the invention. It includes a total of M parallel interleaving units80-1, 80-2, . . . , 80-M, a combiner 81 connected to said interleavingunits, and a control unit 82. Advantageous interleaving units havealready been described above with respect to FIGS. 6 and 7. The combiner81 is adapted to combine (assemble) the output sequences generated bythe interleaving units 80-1, 80-2, . . . , 80-M into said interleavedsequence.

As the skilled person will readily appreciate, M can in general have anyinteger value. In case of M=1, however, a single interleaving unit (ILU)generates the entire interleaved sequence so that no combiner isnecessary. In case of interleavers used in WCDMA applications, typicalvalues for M are four or eight.

The control unit 82 is adapted to control the operations of theinterleaving units and/or the combiner. For this purpose, values ofauxiliary parameters required by the interleaving units are determinedby the control unit on the basis of certain input parameters such as,e.g., the number K of bits in the input sequence.

According to FIG. 8, each ILU is adapted to receive the same inputsequence comprising K bits. However, the first indices ia (and thus thesecond indices ib, too) generated in each interleaving unit vary fromILU to ILU and do not have any common members while making sure that,for each of the K bits of the interleaved sequence, a first index ia isgenerated in one of the M interleaving units.

In a preferred embodiment, each ILU generates an output sequencerepresenting a different one of the M (poly)phases of the interleavedsequence so that the number M of interleaving units could also bereferred to as a sub-sampling factor. For the generation of(poly)phases, the first indices ia generated within the different ILUsmay for example be chosen as followsILU-1 (80-1): ia={0, M, 2*M, 3*M, . . . },ILU-2 (80-2): ia={1, M+1, 2*M+1, 3*M+1, . . . },ILU-3 (80-3): ia={2, M+2, 2*M+2, 3*M+2, . . . },ILU-M (80-M): ia={M−1, 2*M−1, 3*M−1, . . . },provided that the index associated with the first bit of the interleavedsequence is zero. As can be seen from the above example, the firstindices ia of a pair of ILUs differ from each other only by a constantoffset value s so that the above equations can be summarized as follows:ILU-(s+1): ia={s, M+s, 2*M+s, . . . }, s=0, 1, . . . , M−1.  (8)The number of first indices per ILU amounts to N=K/M in this preferredembodiment.

The skilled person will readily appreciate that the number M ofinterleaving units typically is determined as the result of a trade-offbetween the necessary hardware resources and the required operatingfrequency. In general, the higher the value of M, the more hardwareresources (in terms of the number of gates or logic cells, size of ASICarea etc.) are necessary. However, for a given bit rate of the inputsequence, the higher the value of M, the slower each ILU is permitted tooperate. For very high bit rates such as those specified in the WCDMAstandard, the maximum operating frequency for a given hardwaretechnology (such as FPGA, ASIC, DSP) typically entails a minimum valuefor M necessary in order to reduce the operating frequency of each ILUto a realizable level.

In the following, preferred embodiments suitable for an application in aWCDMA turbo code interleaver (cf. the above description with respect tothe prior art) are described. Herein, an interleaving apparatusaccording to FIG. 8 is assumed, wherein M=4 parallel interleaving units(ILUs) 80-1, 80-2, 80-3, and 80-4 are applied in order to generate thefour polyphases of the interleaved sequence. For each of these ILUs, theblock diagram given in FIG. 7 is supposed to hold, wherein the memorymeans is organized in a matrix form having R=10 rows and C=53 columns. Apreferred index generator 71 will be detailed first, while advantageousrow and column index conversion units 74, 75 will be describedafterwards with respect to FIGS. 9 and 10.

Preferably, the index generator 71 includes two counters, a row counterfor generating the first row indices ra={0, 1, . . . , R−1=9} and acolumn counter for generating the first column indices ca={0, 1, . . . ,C−1=52}. Given a value of M=4, it is clear that the “linear” first indexia must be incremented by four in each clock period. While this appliesto all ILUs, each different ILU must use a different offset s rangingfrom 0 for the first ILU 80-1 to M-1=3 for the last ILU 80-4. Forexample, for the first ILU with s=0, we may have ia={0, 4, 8, 12, 16, .. . }. In terms of the first row and column indices ra and ca,respectively, these values of ia translate as follows (cf. equation(6)): ia 0 4 8 12 16 20 24 28 32 . . . 524 528 ra 0 4 8 2 6 0 4 8 2 . .. 4 8 ca 0 0 0 1 1 2 2 2 3 . . . 52 52

From the above example, it can be seen that the row counter in ILU80-(s+1) has to start with the offset value s and that it is incrementedby M in each clock period (where the result is subject to a “modulo R”operation). In contrast, the column counter starts with a zero value andis incremented by one each time the row counter is reduced as a resultof the modulo operation.

The above example applies to a row-wise writing in of the inputsequence. As the skilled person will readily appreciate, in case of acolumn-wise writing in, the parameters relating to rows must be replacedwith corresponding ones relating to columns and vice-versa.

FIG. 9 depicts a block diagram of a preferred embodiment 90 of the rowindex conversion unit 74 shown in FIG. 7 for converting first rowindices ra into second row indices rb. It includes an addressing meansADR 91 and a memory means 92 connected to said addressing means 91.

In the memory means 92, which may be a ROM, an EPROM etc., the inter-rowpermutation patterns P_(A),P_(B),P_(C),P_(D) are stored in the form of alook-up table (LUT). For this purpose, the memory means 92 must be ableto store 55 values (20 for P_(A) and P_(B) each, 10 for PC and 5 for PD,as can be seen from equations (2)), i.e. the LUT must have 55 addresses.Each value can be represented by 5 bits (data width), so that the totalnumber of bits to be stored in the memory means 92 amounts to55*5 bits=275 bits,  (9)only.

Based on the auxiliary parameter P_(X) and a first row index ra, theaddressing means ADR 91 determines an address for appropriatelyaddressing said memory means 92 so that it outputs a correspondingsecond row index rb indicative of the row where the bits of theinterleaved sequence having the row index ra are stored in the memorymeans 73 of FIG. 7. Herein, the auxiliary parameter P_(X) is used toselect one of said permutation patterns P_(A),P_(B),P_(C),P_(D) (by acorresponding offset address value, e.g.), whereas the first row indexra is used to identify a particular value of said selected permutationpattern.

As explained above with respect to the prior art, the value of theauxiliary parameter P_(X) depends on the number R of rows (P_(X)=P_(D)for R=5, P_(X)=P_(C) for R=10) and possibly the number K of bits in theinput sequence (P_(X)=P_(A) or P_(B) for R=20, depending on the value ofK). Based on these parameters, the value of P_(X) can for example bedetermined by a control unit in the interleaving unit or apparatus, suchas the control unit 82 shown in FIG. 8, and then input into the rowindex conversion unit(s) of the interleaving unit(s).

FIG. 10 depicts a block diagram of a preferred embodiment 100 of thecolumn index conversion unit 75 shown in FIG. 7 for converting firstcolumn indices ca (and second row indices rb) into second column indicescb. It includes two memory means 103, 104 and two processing means 101,102. Herein, the first processing means 101 is connected to the memorymeans 103, while the second processing means 102 is connected to thefirst processing means 101 and the memory means 104.

The first processing means 101 determines an auxiliary parameterZ_(rb)(ca) mainly depending on the first column index ca and the secondrow index rb, while the second processing means 102 determines thesecond column index cb on the basis of, among other parameters, thefirst column index ca and the auxiliary parameter Z_(rb)(ca). Herein,the auxiliary parameter Z_(rb)(ca) can be obtained from equation (1)(see the above description relating to the prior art), wherein ca and rbare used in place of the indices i and j, respectivelyZ _(rb)(ca)=c([ca*p(rb)]mod [p−1]), ca=0, 1, . . . , p−2.  (10)In equation (10), p, p(rb), and c( . . . ) denote the minimum prime, amember of the new set {p(0), . . . , p(R−1)}, and a base sequence,respectively, as described above with respect to the prior art. Giventhe fact that the first column index ca is incremented in steps of one(see above), equation (10) can be formulated recursivelyZ _(rb)(ca)=Z _(rb)(ca−1)+k _(rb) with Z_(rb()0)=0,  (11)wherein the following applies:k _(rb) =p(rb)mod(p−1),  (12)if Zvrb(ca)≧p−1, then Z _(rb)(ca)←Z _(rb)(ca)−(p−1).  (13)

Herein, the auxiliary parameter k_(rb) depends on rb, p, and P_(X) (cf.the above description of FIG. 9). The values of k_(rb) are thereforepre-calculated according to equation (12) for all possible values of rb,p, P_(X), and stored in the memory means 103 (ROM, EPROM etc.) in theform of a look-up table LUTk. For this purpose, the memory means 103must be able to store 55 values (20 for P_(A) and P_(B) each, 10 forP_(C) and 5 for P_(D), as can be seen from equations (2)) for each ofthe 52 possible values of p, i.e. the LUTk must have 55*52=2860addresses. For an assumed maximum p value of 257, the data width needsto be 8 bits (max. value 255) so that the total number of bits to bestored in the memory means 103 amounts to2860*8 bits=22880 bits.  (14)

Similarly, the base sequences c( . . . ) as described above with respectto the prior art are pre-calculated for all 52 possible values of p andstored in the memory means 104 (ROM, EPROM etc.) in the form of alook-up table LUTc. Note that for a particular value of p, thecorresponding base sequence comprises p values. For this reason, thememory means 104 must be able to store a total of p₁+p₂+ . . . +p₅₂=6328values, i.e. the LUTc must have 6328 addresses. Assuming again a maximump value of 257, the required data width is 9 bits (max. value 256) sothat the total number of bits to be stored in the memory means 104amounts to6328*9 bits=56952 bits.  (15)

Operatively, on the basis of the input parameters P_(X) and p, the firstprocessing means 101 addresses the memory means 103 so as to readtherefrom the 5, 10, or 20 corresponding values of k_(rb) for allpossible values of rb. For a given value of ca, these values of k_(rb)are then added to the corresponding values Z_(rb)(ca−1) according toequation (11) in order to determine, again for all possible values ofrb, the values of Z_(rb)(ca), while observing equation (13). Finally,one of the Z_(rb)(ca) values is selected by a multiplexer, e.g., asindicated by the input parameter rb, and then output by the firstprocessing means 101.

Depending on the values of the first column index ca and the minimumprime p, the second processing means 102 determines the second columnindex cb according to Table 1, wherein R and C denote the number of rowsand columns, respectively, in the memory means 73 of FIG. 7. TABLE 1case cb generation a) C = p cb = LUTc(Z_(rb)(ca)) for ca = 0, 1, ...,C−2 cb = 0 for ca = C−1 b) C = p+1 cb = LUTc(Z_(rb)(ca)) for ca = 0, 1,..., C−3 cb = 0 for ca = C−2 cb = p for ca = C−1 IF K = R × C cb = p forca = 0 AND rb = R−1 cb = LUTc(Z_(rb)(ca)) for ca = 1, 2, ..., C−3 cb = 0for ca = C−2 cb = LUTc(Z_(rb)(0)) for ca = C−1 c) C = p−1 cb =LUTc(Z_(rb)(ca))−1 for ca = 0, 1, ..., C−1

If necessary according to Table 1, the memory means 104 (LUTc) isaddressed appropriately using the Z_(rb)(ca) value (or Z_(rb)(0)) outputby the first processing means 101 as an index to the appropriate basesequence c( . . . ) so as to retrieve the second column index cbindicative of the column where the bits of the interleaved sequencehaving the row index ra and the column index ca are stored in the memorymeans 73 of FIG. 7.

As the skilled person will readily appreciate, the memory means 92, 103,and 104 shown in FIGS. 9 and 10 as parts of the row and column indexconversion units, respectively, can of course be placed outside these(then purely logic) units but inside the index conversion unit 72 ofFIG. 7, or even outside the index conversion unit (62,72) but inside theinterleaving unit ILU (60,70) in FIG. 6 or 7. In the latter case, aunified memory means (including the memory means 92, 103, and 104)connected to the index conversion unit (62,72) could be added inside theILU (60,70). In addition, the index conversion unit would then beadapted to perform logic operations only so that it could be referred toas a logic mit.

When M>1 parallel interleaving units 80-1, . . . , 80-M are providedaccording to FIG. 8, the question arises whether a single unified memorymeans (including the memory means 92, 103, and 104 for all ILUs) couldbe placed outside the interleaving units and connected thereto so thatno memory means would be required inside the interleaving units.Although this is possible in principle, this measure increasesimplementational complexity. Since all M interleaving units would haveto access the single unified memory means within each cycle, this memorymeans would be required to either have M ports allowing for Msimultaneous read accesses or to be operable at M times the originaloperating frequency. In both cases, hardware complexity increases sothat, normally, a single unified memory means will not be realized.However, interim solutions including both a common (large) “top-level”memory means outside the interleaving units and a (small) ILU-internalmemory means in each ILU may be advantageous, as will be describedbelow.

In the following, it is evaluated in how far the requirements formulatedin the above section on the prior art are met, in the example consideredabove, by the interleaving approach according to the invention, asdescribed above with respect to FIGS. 4 to 10.

From the above description with respect to FIGS. 9 and 10, it can beconcluded that an interleaving unit (ILU) according to FIG. 6 or 7requires memory means 92, 103, and 104 capable of storing a total of(cf. equations (9), (14), and (15))275 bits+22880 bits+56952 bits=80107 bits  (16)in addition to the “data” memory means required anyway (memory means63/73 of FIG. 6/7).

Compared with approach A2 (as described above with respect to the priorart) requiring a position memory capable of storing 5297500 bitsaccording to equation (5), the interleaving unit according to theinvention thus reduces the memory requirement by a factor of5297500/80107=66, or equivalently, more than 98%.

With respect to the delay requirement, the following can be stated. Oncethe input sequence has been written into the memory means 63,73, nofurther access to said memory means 63,73 is necessary before readingout the first bit of the interleaved sequence, because, according to theinvention, the process of determining indices (reflecting the necessarypermutations) has been decoupled from the actualpermutation/interleaving operations.

At the limit, the delay between “last bit in” and “first bit out” can bereduced to almost zero by making sure (through an appropriate timing)that the second indices (ib; rb,cb) for the first bit of the interleavedsequence are available at the address inputs of the memory means 63,73by the time the last bit of the input sequence is written into thememory means 63,73 so that, one cycle later, the first bit of theinterleaved sequence can be read out from the corresponding position ofthe memory means 63,73.

With respect to approach A1 as described in the above section on theprior art, wherein the bits of the input sequence are written into thememory means two times in addition to the initial writing-in, a dramaticreduction in delay is thus achieved by the invention.

In comparison with approach A2, the invention achieves equally gooddelay properties. In contrast with A2, however, these good delayproperties are not achieved at the expense of increased memory sizes, asshown above.

When incorporating M parallel interleaving units (ILUs) according to theinvention into an interleaving apparatus as shown in FIG. 8, a trade-offinvolving the total hardware effort, the operating frequency and/or theinput/output bit rate is possible. Either the operating frequency of theILUs can be reduced by a factor of M while still being able to cope withthe original bit rate, or alternatively, the bit rate can be increasedby a factor of M if the operating frequency remains unchanged. In otherwords, this means that high bit rates, as required by advancedcommunication standards such as WCDMA, can be coped with conveniently(by using parallel ILUs according to FIG. 8) due to the relatively smallimplementational effort associated with each ILU according to theinvention. Assuming that, according to equation (16), each ILU requiresmemory means capable of storing a total of 80107 bits, an interleavingapparatus comprising M such ILUs will require storage ofM*80107 bits,  (17)which, for typical values of M (4, 8, or 16) is still well below thememory sizes required by approach A2, let alone the fact that, normally,the memory sizes required by A2 also multiply by a factor of M as aresult of parallelization due to the multiple access problem describedabove.

It is to be noted that in a parallel configuration according to FIG. 8,the required total memory size can be reduced well below the valueindicated in equation (17). This is due to the fact that in the memorymeans 103, 104, base sequences and k_(rb) values are stored for all 52possible values of the minimum prime p, although only those basesequences and k_(rb) values for a particular p value are needed by theprocessing means 101, 102 and thus by the interleaving units forinterleaving a given input sequence.

For this reason, a common (large) “top-level” memory means adapted tostore the base sequences and k_(rb) values for all possible values of pcould be provided outside the interleaving units of FIG. 8, while itwould be sufficient for each ILU to include a small memory means adaptedto store only those base sequences and k_(rb) values required by theprocessing means 101, 102 for a particular p value. Operatively, theILU-internal small memory means would then download, during an initialphase, the base sequences and k_(rb) values required for a particular pvalue from the common top-level memory means. As all ILUs would downloadthe same blocks of base sequences and k_(rb) values (p is the same forall ILUs), this would not pose any problems of multiple accesses to thecommon top-level memory means. In this way, the size of the memory means103 in each ILU (inside or outside the index conversion unit) can bereduced by a factor of 52, leading to22880 bits/52=440 bits  (18)according to, and in comparison with, equation (14), while the size ofthe memory means 104 in each ILU (inside or outside the index conversionunit) can be reduced to257*9 bits=2313 bits,  (19)which is the number of bits necessary to store the longest base sequencehaving 257 values. Thus, the small ILU-internal memory means must beadapted to store440 bits+2313 bits=2753 bits,  (20)so that the entire interleaving apparatus according to FIG. 8 requiresstorage of80107 bits+M*2753 bits,  (21)in contrast to equation (17). Herein, it has been assumed that theinter-row permutation patterns are also stored only once in the commontop-level memory means rather than in each ILU (cf. the memory means 92of FIG. 9), although the effect in memory reduction is negligiblecompared with the one obtained by storing only the required basesequences and k_(rb) values in each ILU. Finally, it is to be noted thatthe overall memory size indicated in equation (21) is well inferior tothe one shown in equation (17) for all values of M≧2.

Further, from the description given above with respect to the presentinvention it is clear that the present invention also relates to acomputer program product directly loadable into the internal memory of adigital communication unit (such as a transceiver or transmitter of abase station or a mobile phone etc.) for performing the steps of theinventive interleaving approach in case the product is run on aprocessor of the digital communication unit.

Therefore, this further aspect of the present invention covers the useof the inventive concepts and principles for optimised interleavingwithin, e.g., mobile phones and base stations adapted to futureapplications. The provision of the computer program products allows foreasy portability of the inventive concepts and principles as well as fora flexible implementation in case of re-specifications of theinterleaving scheme(s).

The foregoing description of preferred embodiments has been presentedfor the purpose of illustration and description. It is not intended tobe exhaustive or to limit the invention to the precise form disclosed.Obvious modifications or variations are possible in the light of theabove technical teachings. The embodiments have been chosen anddescribed to provide the best illustration of the principles underlyingthe present invention as well as its practical application and furtherto enable one of ordinary skill in the art to utilize the presentinvention in various embodiments and with various modifications as aresuited to the particular use contemplated. All such modifications andvariations are within the scope of the invention as determined by theappended claims.

LIST OF IMPORTANT PARAMETERS

-   C: Number of columns in the interleaving matrix-   Ca: First column indices-   cb: Second column indices-   c(i): Base sequence-   {cj(i)}: Intra-row permutation pattern for row index j-   ia: First indices-   ib: Second indices-   K: Number of bits in the input sequence-   k_(rb): Auxiliary parameter for the recursive determination of    Z_(rb)(ca)-   M: Number of parallel ILUs in the interleaving apparatus;    subsampling factor-   N: number of succeeding bits of the interleaved sequence, for which    indices are generated in the index generator/generating step.-   p: minimum prime-   P_(A),P_(B), . . . : Inter-row permutation patterns-   P_(X): Indication of a particular inter-row pattern-   R: Number of rows in the interleaving matri-   ra: First row indices-   rb: Second row indices-   Z_(rb)(ca): Indices to base sequences

LIST OF ABBREVIATIONS

-   3G: third generation-   3GPP: third generation partnership project-   ASIC: Application specific integrated circuit-   BS: Base station-   DSP: Digital signal processor-   ETSI: European Telecomm. Standardization Institute-   FDD: Frequency division duplex-   FPGA: Field programmable gate array-   GSM: Global system for mobile communications-   IL: Interleaver-   ILU: Interleaving unit-   IS-95: Interim Standard 95-   LUT: Look-up table-   MT: Mobile terminal/station-   MUX: Multiplexer-   PDC: Personal digital cellular (system)-   PSTN: Public switched telephone network-   RAM: Random access memory-   ROM: Read-only memory-   TC: Turbo code(r)-   TDMA: Time division multiple access-   TIL: Turbo Interleaver-   TS: Technical specification-   WCDMA: Wideband code division multiple access

1-20. (canceled)
 21. A method, for use in a digital communicationsystem, for interleaving input data having K≧2 bits according to aninterleaving scheme into an interleaved sequence, said method comprisingthe steps of: a) storing the input data in a first memory means; b)generating first indices of N succeeding bits of the interleavedsequence; c) converting, according to an inverse of said interleavingscheme, said first indices into second indices indicative of thepositions where said N succeeding bits of the interleaved sequence arestored in said first memory means; and, d) reading out said N succeedingbits from said positions in said first memory means, thereby generatingat least part of said interleaved sequence.
 22. The method according toclaim 21, wherein: said first memory means is organized in a matrix formcomprising rows and columns; said first indices comprise first rowindices and first column indices; and, said second indices comprisesecond row indices and second column indices; and, wherein said step ofconverting comprises the steps of: converting said first row indicesinto said second row indices so that inter-row permutation operationsaccording to said interleaving scheme are performed when said step ofreading out is executed; and, converting said first column indices intosaid second column indices so that intra-row permutation operationsaccording to said interleaving scheme are performed when said step ofreading out is executed.
 23. The method according to claim 22, whereinsaid step of converting said first row indices comprises the steps of:storing at least one permutation pattern defining said inter-rowpermutation operations in a second memory means; and, addressing saidsecond memory means with addresses depending on at least said first rowindices, causing said second memory means to output said second rowindices.
 24. The method according to claim 22, wherein said step ofconverting said first column indices comprises the step of: convertingsaid first column indices and said second row indices into said secondcolumn indices so that intra-row permutation operations depending on arow index are performed when said step of reading out is executed. 25.The method according to claim 24, wherein said step of converting saidfirst column indices comprises the steps of: determining base sequenceindices depending on said first column indices and said second rowindices by adding index increments depending on said second row indicesto previously determined base sequence indices; and, determining saidsecond column indices on the basis of at least said first column indicesand said base sequence indices.
 26. The method according to claim 25,wherein said step of converting comprises the steps of: storing at leastsaid index increments in a third memory means; storing at least one basesequence specified by said interleaving scheme in a fourth memory means;wherein, said step of determining base sequence indices is adapted toaddress said third memory means so as to read therefrom said indexincrement; and, said step of determining said second column indices isadapted to address said fourth memory means so as to read therefromcorresponding values of said at least one base sequence.
 27. The methodaccording to claim 21, wherein N is selected to have a value of K, andwherein said first memory means is adapted to generate said interleavedsequence when said N succeeding bits are read out from said positions.28. The method according to claim 21, wherein N is selected to have avalue of K/M with M≧2 denoting a sub-sampling factor, and wherein saidfirst memory means is adapted to generate an output sequencerepresenting one of M polyphases of said interleaved sequence when saidN succeeding bits are read out from said positions.
 29. The methodaccording to claim 21, wherein said steps of generating and convertingare executed, at least partially, before said step of storing.
 30. Aninterleaving apparatus, for use in a digital communication system, forinterleaving input data having K≧2 bits according to an interleavingscheme into an interleaved sequence, said apparatus comprising: a) anindex generator for generating first indices of N succeeding bits of theinterleaved sequence; b) an index conversion unit connected to saidindex generator for converting, according to an inverse of saidinterleaving scheme, said first indices into second indices indicativeof the positions where said N succeeding bits of the interleavedsequence are stored in a first memory means; and, c) first memory meansconnected to said index conversion unit, wherein said first memory meansis adapted to store said input sequence and to generate at least part ofsaid interleaved sequence when said N succeeding bits are read out fromsaid positions.
 31. The interleaving apparatus according to claim 30,wherein: said first memory means is organized in a matrix formcomprising rows and columns; said first indices comprise first rowindices and first column indices; said second indices comprise secondrow indices and second column indices; and, wherein said indexconversion unit includes: a row index conversion unit for convertingsaid first row indices into said second row indices so that inter-rowpermutation operations according to said interleaving scheme areperformed when said N succeeding bits are read out from said positionsin said first memory means; and, a column index conversion unit forconverting said first column indices into said second column indices sothat intra-row permutation operations according to said interleavingscheme are performed when said N succeeding bits are read out from saidpositions in said first memory means.
 32. The interleaving apparatusaccording to claim 31, further comprising: second memory means forstoring at least one permutation pattern defining said inter-rowpermutation operations; and, wherein said row index conversion unitincludes addressing means for addressing said second memory means withaddresses depending on at least said first row indices, thereby causingsaid second memory means to output said second row indices.
 33. Theinterleaving apparatus according to claim 31, wherein said column indexconversion unit comprises: means for converting said first columnindices and said second row indices into said second column indices sothat intra-row permutation operations depending on a row index areperformed when said N succeeding bits are read out from said positionsin said first memory means.
 34. The interleaving apparatus according toclaim 33, wherein said column index conversion unit includes: firstprocessing means for determining base sequence indices depending on saidfirst column indices and said second row indices by adding indexincrements depending on said second row indices to previous basesequence indices; second processing means, connected to said firstprocessing means, for determining said second column indices on thebasis of at least said first column indices and said base sequenceindices determined by said first processing means.
 35. The interleavingapparatus according to claim 34, further comprising: third memory means,connected to said first processing means, for storing at least saidindex increments; fourth memory means, connected to said secondprocessing means, for storing at least one base sequence specified bysaid interleaving scheme; wherein: said first processing means isadapted to address said third memory means so as to read therefrom saidindex increments; and, said second processing means is adapted toaddress said fourth memory means so as to read therefrom correspondingvalues of said at least one base sequence.
 36. The interleavingapparatus according to claim 30, wherein N is selected to have a valueof K, and wherein said first memory means is adapted to generate saidinterleaved sequence when said N succeeding bits are read out from saidpositions.
 37. The interleaving apparatus according to claim 30, whereinN is selected to have a value of K/M with M≧2 denoting a sub-samplingfactor, and wherein said first memory means is adapted to generate anoutput sequence representing one of M polyphases of said interleavedsequence when said N succeeding bits are read out from said positions.38. The interleaving apparatus according to claim 37, comprising: M≧2interleaving units, each adapted to receive said input sequence and togenerate an output sequence representing a different one of said Mpolyphases; a combiner connected to said M interleaving units forcombining the output sequences generated by said M interleaving unitsinto said interleaved sequence; and, a control unit for controlling theoperations of said M interleaving units and said combiner.
 39. Theinterleaving apparatus according to claim 38, further comprising: fifthmemory means, connected to said M inter-leaving units, for storing atleast one of a complete set of base sequences according to theinterleaving scheme and a complete set of base sequence indexincrements.